19 Feb
2008
19 Feb
'08
3:54 p.m.
Antonio Carlini wrote:
The ones I have that _don't_ do ECC would indeed
be 16Mx64. I'd not want
the
design to use the ECC, just not object to it (assuming it would even
notice).
The ECC is done with a couple of extra 'parity' bits IIRC...
Or that's the impression I got when I looked at the standard DIMM pinouts.
I get exactly the same story from the VLSI guys at
work (although they
usually claim to have run out of gates first :-)).
That's what happened with the Mk1 design with the Xilinx CPLD - 288
macrocells, all filled up. And that was with only two thirds of the core logic.
If the memory isn't going to be socketed, then
I'll not worry about it.
Nope, no socket, just a single chip.
Although we do use Altera stuff at work ... must go
and ask about
samples
some time ...
I just got my four Altera FPGAs this morning - shame whoever packaged them
managed to shove them into a waffle-pack that was far too small, bending the
pins on three of the four chips, two to the point where pins broke off.
One of them is OK, but I'm still going to be having words with Farnell over
this nice little mess.. probably something to the effect of "whose idea was it
to stuff a bunch of QFP144 chips into a package designed for QFP48s?"
Just can't get the staff. Or the suppliers. <grin>
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