3 Jul
2008
3 Jul
'08
10:40 a.m.
On Thu, Jul 03, 2008 at 12:57:43PM -0400, Dave McGuire wrote:
I've only worked with 41256s design-wise. We
used 8207 DRAM
controllers, which were great in terms of functionality, but good
heavens did we have problems with noisy power on those boards. I
never want to go through that again. Those refresh spikes had such
fast rise times (in ca. 1987 terms) that short, low-inductance paths
to the bypass capacitors within the DRAM array turned out to be very
important.
My design experience goes back only a tad farther - to 4164s and
74S409 DRAM controllers in a 128K array on the COMBOARD2 (circa
1983-1984). I didn't design it, but I was working with the
engineers when we had to figure out why it didn't work reliably
(we had to add 33Ohm resistors inline with the CAS/RAS lines
to dampen undershoot - a topic which has come up here in the
past once or twice).
I just mean putting some decent bypassing
electrically close to
the board; presumably there are already a reasonable number of bypass
capacitors in the DRAM array.
Yep. The PET board has two caps per DRAM chip (+12V and +5V) right
there next to the chips.
Steven Canning said the supply that's
affected worst by refreshing is +12V...I didn't know that; if that's
the case then you shouldn't have to worry all that much about
bypassing -5V anyway.
I didn't know about the larger noise on +12V either, but for this
particular application, I don't recall much else besides the RAM
array hanging off of the +12V line. As long as the noise doesn't
screw up refresh cycles, I don't think it will be a problem.
Cheers,
-ethan
--
Ethan Dicks, A-333-S Current South Pole Weather at 3-Jul-2008 at 17:20 Z
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Ethan.Dicks at usap.gov http://penguincentral.com/penguincentral.html