2 Jan
2019
2 Jan
'19
12:09 p.m.
On Wed, Jan 02, 2019 at 02:37:44PM -0500, Paul Koning via cctalk wrote:
Which then reminds me further of the Coldfire processor which
*did* remove the more complex instructions from the chip!
On Jan 2, 2019, at 2:31 PM, Chuck Guzis via
cctalk <cctalk at classiccmp.org> wrote:
On 1/2/19 10:44 AM, Guy Sotomayor Jr wrote:
That reminds me of the Motorola 68040. I used that at DEC in a high speed switch
(DECswitch 900 -- FDDI to 6 Ethernet ports). When studying the instruction timings, I
realized there is a "RISC subset" of the instructions that run fast, a cycle or
so per instruction. But the more complex instructions are much slower. So the conclusion
for a fastpath writer is to use the RISC subset and pretend the fancy addressing mode
instructions do not exist. Also, recall that there are different forms of
micro-code: horizontal
and vertical. I think that IBM (in the S/360, S/370, S/390, z/Series)
uses the term micro-code for horizontal micro-code and millicode
for vertical microcode.
On the CDC STAR-100, "microcode" as such was a relatively recent concept
and the designers went overboard, mostly because of an ill-defined
customer base (hence, BCD and other commerical-class instructions, like
translate, edit and mark, etc.). The STAR is basically a RISC-type
vector architecture with a pile of microcoded instructions bolted on.
...
For a compiler writer, or even an assembly coder, this was more of a
problem--which combination of instructions could be used to the greatest
effect? And why do I have to have the hardware manual on my desk to
look up instructions?
paul
Diane
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