14 Dec
2001
14 Dec
'01
10:41 p.m.
I don't think the DART would have been such a mess. If you AND (/IOR and /IOW)
you get a useable IORQ, not that you really need it, since it's only used in
conjunction with M1 to signal the mode-2 interrupt acknowledge, which wouldn't
occur in this case. If the device is selected I'm not at all sure it cares one
iota whether IORQ is active.
see below, plz.
Dick
----- Original Message -----
From: "Peter C. Wallace" <pcw(a)mesanet.com>
To: <classiccmp(a)classiccmp.org>
Sent: Friday, December 14, 2001 6:45 PM
Subject: Re: MITS 2SIO serial chip?
Not exactly direct. you do have to invert the ALE to form the DataStrobe or
whatever that signal was. I always liked the 8250 because it was a 1-part
solution to a problem otherwise using two or more parts. It is a convenient
part for the ISA, but since the ISA presents all the other signals, /IOR, /IOW,
etc, from which you can derive the required signals in a 16L8 anyway, which is
what most of them used for decoding the addresses, you could make whatever
signals you needed.
which
On Fri, 14 Dec 2001, Richard Erlacher wrote:
> <snip>
> > Dart is Z80 bus, (like an Async only SIO) not Intel. Have to take your
> > word on the TCM78808 - sure it was available in 1981?
> >
> My old TI datasheets are hiding, so I can't verify what was when.
>
> I'm not sure exactly what difference it makes whose bus the serial I/O chip
is
> designed for when the whole bunch of devices use
essentially the same
signals to
> get the job done. The DART doesn't work much
differently than any other
serial
> I/O device so long as you don't attempt to
use some of its unique features.
It
> seems to me that it takes about the same quantity
of machinations to make
the
> 8250, which is also not ideally suited to the ISA
bus, work on the ISA bus,
as
> it would take to make a Z80 DART or an 8251 or a
2651 do the job. Likewise
for
> the 2681/68681. No matter what you need, a small
PAL will do the trick.
That
certainly
wasn't lost on I/O board makers.
The 8250 is a direct ISA bus interface (no logic other than decode needed)
The DART would be a mess, using the Z80s M1,IORQ and all that. (not that
there's anything wrong with the Z80 way)
> >
> I checked the actual board, and the PLCC part that I designed in to the
board
I
> was thinking about. It turns out the early
version used a few 68-pin PLCC
> sockets, and, in fact, there were no 44-pin PLCC's on that board. The part
in
> the PLCC socket, BTW was not a PLCC, but a JEDEC
'C' package. Though there
was
> paper for the PLCC, the only parts used on the
prototype board in that
> application were in the JEDEC 'C' package. Fortunately, unlike the JEDEC
'A'
> package, (that leadless single-sided ceramic chip
carrier in which i80186's
and
> i80286's were commonly used) the 'C'
package would easily work in a PLCC
socket.
A later
version, however, did, indeed have the 8250's in the PLCC-44 on it.
Sure, there are 8250's (and 16450's and 16550's etc etc) in PLCCs, just
not in 1981...
> >
> I really don't think practical considerations such as cost entered into the
> early decision stream in the PC development, once it reached the point at
> upper management was prepared to pull the plug if
at least one milestone
wasn't
> met. The way I heard the story from some of the
guys who worked at Boca was
> that there wouldn't have been an IBM PC if Intel hadn't presented the guys
with
> a board-level prototype of the '188 (not an
application of the '188). While
> it's easy enough to believe that the entire project had deteriorated into a
> "Chinese fire drill," I can't believe that Intel would have had the
brains
to
> present a canned solution to them in time to pull
the chestnuts from the
fire.
>
> Dick
>
> > > > > ----- Original Message -----
> > > > > From: "Peter C. Wallace" <pcw(a)mesanet.com>
> > > > > To: <classiccmp(a)classiccmp.org>
> > > > > Sent: Friday, December 14, 2001 12:28 PM
> > > > > Subject: Re: MITS 2SIO serial chip?
> > > > >
> > > > >
> > > > > > On Fri, 14 Dec 2001, Gene Buckle wrote:
> > > > > >
> > > > > > > > NS* did use them as did many others. The worst
chip was
> > > > > > > > the 8250.
> > > > > > >
> > > > > > > Which makes me wonder what possessed IBM to pick it
for the PC.
> > > > > > >
> > > > > > > g.
> > > > > >
> > > > > > The same reason they chose active high edge triggered
interrupts
on
the
Peter Wallace
Mesa Electronics
> > > > bus (wrong on both counts)
> > > >
> > > > The same reason they used 8 bits of an 8255 to read the KB shift
register
> >
> that had a (unused) tri-state
> > >
> > > The PC = A horrible, amateurishly designed kluge
> > >
> > >
> > > Peter Wallace
> > >
> > >
> >
> >
>
> Peter Wallace
> Mesa Electronics
>
>
Peter Wallace
Mesa Electronics