Hi
Well that's seems to define the 11/84.
How does this all apply to the 11/94
(which is the real problem)
Rod
-----Original Message-----
From: cctech-bounces at
classiccmp.org
[mailto:cctech-bounces at
classiccmp.org] On Behalf Of Johnny Billquist
Sent: 21 May 2007 21:41
To: On-Topic and Off-Topic Posts; Pete Turnbull
Subject: PDP-11/84, PMI and Q-bus
Okay, since this topic have become a subject of much discussion and some
diverse opinions, I decided to really read the manuals to try to find
the bottom of this all.
My main source of information here have been the "KDJ11-B CPU Module
Users's Guide". EK-KDJ1B-UG-001
Now, to start with the position of the CPU card in an 11/84.
Chapter 7, section 7.2. Page 7-1:
"7.2 PMI INTERFACE
The PMI interface signals are defined as the PMI bus master signals, the
PMI slave signals and the PMI Unibus adapter signals. These interface
signals are assigned to the C and D rows of the backplane and are
defined as the interconnect bus. The PMI interface signals on the C/D
bus are normally assigned two pins to provide an interconnection between
the slots. The KDJ11-B module is only assigned one pin and therefore its
position in the backplane is critical. The LSI bus signals that are used
with the PMI protocol use the A and B rows of the backplane defined as
the LSI bus."
Now, if Pete is correct in that the PMI bus on the 11/84 really goes to
both pins on all slots, then it should be okay to place the CPU in any
slot. I haven't tried that, but I might when I have the time. I suspect
he's right since otherwise I would have expected the CPU to be in slot
3. But DEC could be doing some fancy wiring... :-)
The fact that the placement is critical is obvious if we talk about
Q-bus systems, and I suspect the comment is written from that point of
view.
As for wether Q-bus memory (or any other Q-bus peripherial) will work,
I'll quote some signal descriptions.
Chapter 7, page 7-4. Table 7-3 PMI Unibus Adapter Signals
"Pin: CF1 Mnemonic: PUBSYS L PMI Unibus System
In a Unibus system, PUBSYS L is asserted by the UBA to direct the
KDJ11-B to follow PMI protocol for all data transfers, wether the PSSEL
L is asserted or not. LSI-11 bus protocol is disabled for all PMI
devices when PUBSYS L is asserted.
In an LSI-11 system, PUBSYS L is always negated. If PSSEL L is negated,
the KDJ11-B follows LSI-11 protocol and the PMI memory then responds to
the LSI-11 protocol by the LSI DMA devices."
Chapter 7, page 7-5. Table 7-4 LSI Bus Signals
"Pin: AF2 Mnemonic: BRPLY L Reply
During PMI cycles, BRPLY L is asserted by the KDJ11-B and the PMI slave
to prevent the next bus master from gaining control of the bus too soon.
In a Unibus system, BRPLY L is asserted by the UBA as a slave response
during the PMI DATOB cycle and interrupt DATI cycle.
*** NOTE ***
The PMI memory slave modules in a Unibus system must have BRPLY L
disabled at all times.
Pin: AH2 Mnemonic: BDIN L Data Input
The BDIN L signal is only used in PMI Unibus systems during interrupt
grant cycles. The KDJ11-B asserts BDIN L after it gates the interrupt
priority, BDAL bits <3:0>, onto the bus. The UBA then latches the
interrupt priority data using the leading edge of BDIN L.
Pin: AM2 Mnemonic: BIAKI L Interrupt Acknowledge In
Pin: AN2 Mnemonic: BIAKO L Interrupt Acknowledge Out
These signals are only used in PMI Unibus systems during the interrupt
grant cycles. The KDJ11-B asserts the BIAKI L signal, and the UBDA
acknowledges it by asserting one of the Unibus bus grant signals.
Pin: BB1 Mnemonic: BPOK H Power OK
This signal is only used in PMI Unibus systems for the Unibus
power-up/power-down protocol. This signal is asserted and negated by the
UBA in response to the Unibus AC LO signal. The assertion of AC LO may
be prolonged by the Unibus devices or the PMI memory during power-up."
I could go on describing more details on how these signals are used,
since it's all described in the manual. Suffice to day that the KDJ11-B
*knows* when it's in a Unibus system (i.e 11/84) and will not behave
like a normal Qbus. First of all, it will always use PMI protocol to
access memory, no matter what the memory might claim. Second, interrupt
handling is done differently, since all interrupts are expected to be
dealt with via the UBA.
There are also schematics for different signals in the manual, and you
can clearly find the PUBSYS L signal included in some decoder path as a
way to force a specific behaviour independent of other signals that
might exist.
Now, can we now accept that it's not a Q-bus in the 11/84? :-)
Johnny
--
Johnny Billquist || "I'm on a bus
|| on a psychedelic trip
email: bqt at softjar.se || Reading murder books
pdp is alive! || tryin' to stay hip" - B. Idol