9 Nov
2005
9 Nov
'05
4:42 p.m.
Holger Veit wrote:
woodelf wrote:
Well everybody likes 12 bits...
Which is what I don't understand from my experiences with my own CPU
long ago. 16 bit would be okay and maybe even more bits, but I decided
against classical 4, 8 or 12 bits those days, although these sizes
were quite popular then for "real" CPUs. The point is that I didn't
want to have sophisticated instruction decoding logic, this disallowed
multiple word instructions. I knew about microprogramming, of course,
but this were out of reach because of lacking facilities to burn PROMs
(I was a pupil then).
I thought that is why they went to 16 or 18 bits word length for the
small machines..
For memory addresses and immediate operands, this
meant a single
instruction should hold enough address or data bits. With 12 bits you
are restricted to too few possible instructions or too few address
bits (4 bit instruction or 8 bit address/immediate data was not enough
for my ambitious plans. 16 bit were suitable even if it required two
"load immediate" instructions (for the low and the high byte). However
the first architecture had 16 bit instructions but an 8 bit data path
only (except the separate 12 bit address increment/index logic).
The current 18 bit computer I a building using CPLD's has a 128 cell
CPLD for the 9 bit slices and
a 128 cell CPLD for the CONTROL unit. The biggest pain is byte swapping
for character data,
another 84 pin CPLD for memory. The 5 th CPLD is a glue chip with the
IDE Interface , 8 bit I/O
buss for the 6821's and 6850's and a 128 x 18 bootstrap rom. I
suspect if the design was done
in TTL the control section would be 1/3 with the other 2/3's data path
for about 300 SSI chips.
Holger
The fun part of this design is I am doing the cpu structure as
monolithc cpu in a 48 pin
package and the memory bus swap buffer as a undefined 48 pin package.
This design
is about just after the z80 or 6809 came out but before the 16 bit cpu's
with large memory
addressing. The next version could be real TTL with a MMU and dynamic
memory.
( 64k and 256k chips -- no 16k chips from the 70's era )