PDP-8s and -10s

Andy> As the 6600 was entirely built with discrete components, not Andy> chips, and yet had to be physically relatively compact, I doubt Andy> if it had much more than say 20,000-25,000 gates. Nowadays Andy> that isn't anywhere near high end of the FPGA ranges. It's quite a lot more than 20k gates. Looking at the diagrams in Thornton -- the individual logic modules are surprisingly dense. I counted 25 gates on one of the adder modules (and it's more than that if you use FPGA "gate equivalents" since many of them had more than 2 inputs). He also says that each chassiss can hold 756 logic modules (18 rows at 42 modules per row). And there are 7 logic chassis in a 6600 (8 more are memory, one is unused). So if an average module is 20 gates that gives 100k gates. Cray always was much better at densely packed logic than everyone else. Check out Thornton's book (it's on bitsavers). Chapter 3 nicely shows the packaging and how it gets so much stuff in so little space. Lastly, the conversion I was reporting involved putting the central memory on-chip too; without that, you'd either lose a lot of performance or use up a whole lot of pins for wide memory. paul