23 Nov
2007
23 Nov
'07
10:42 a.m.
Roy J. Tellason wrote:
No No No ... Use the CPLD design I am working on ( No floating point :( )
and have a machine at 5.33 MHZ (750 ns memory cycle).
See faster than a Pee-cee at 4.77 MHZ :)
Hard to say if it is faster than a Pee-cee as who knows how fast the PC
runs with its pre-fetch buffer.
Ben alias woodelf
PS. And with every byte you get a free extra nibble over the PC.
With octal digits your 256 KB of memory looks even more impressive
than 5 hexadecimal digits. Well ok you could have 23 bits of address
but I want to keep this in era of 16K dram chips and 256Kb is very large.
....but if
I'd done that I'd have used a 68K instead of that Intel garbage
IBM chose.... ;-)
Ditto.