18 Mar
2010
18 Mar
'10
3:33 p.m.
Tony Duell wrote:
Sorry to barge in,
but I don't think is exactly correct. On most ARM
systems these days, for
example, there are multiple hardware breakpoints inside the jtag debug
logic which are
not intrusive. They don't perterb the instruction stream at all until
they are hit.
And, on some ARM SOC's there is an internal trace buffer which is also
not intrusive,
and is "free" in terms of timing (i.e. it doesn't slow anything down).
Both have saved me a few times.
-brad
--
-----------
Brad Parker
Heeltoe Consulting
http://www.heeltoe.com
781-483-3101
But most JTAG
debuggers allow for breakpoints/watches, register
examination/alteration, single-step, etc. And there's at least one
debug interface that uses a one-wire connection to the RESET pin, so
you get to use all of the I/Os.
Sure..
But there are several problems with that approach. The main one is that a
breakpoint is intrusive, it changes the behaviour of the system.