On Thursday (10/25/2012 at 08:02AM -0400), David Riley wrote:
On Oct 25, 2012, at 1:33, Dave McGuire <mcguire at
neurotica.com> wrote:
Is there a speed penalty for using /OE instead of
the gate's actual input?
Not really. Tpd and the output enable times are roughly
the same. I don't see output rise/fall times in any of
the datasheets I've found, but that doesn't mean
they don't exist; there are plenty more brands to check.
Wondering if you are considering the voltage level translations to
modern FPGA and micros in whatever transceiver scheme is selected too?
ie, if we put down 3.3V or 1.8V modern parts, how do we get to/from the
5V domain on the backplane?
I haven't had a chance to look at all the Tpd characteristics, but TI
have a lot of parts that do this kind of thing. eg,
http://www.ti.com/product/sn74gtl2003
and an app note here,
http://www.ti.com/lit/scea006
Chris
--
Chris Elmquist