cctech Digest, Vol 78, Issue 3

That's the one. A more stupid design decision is hard to imagine! Not having individual direction cotrnol bits for each I/O line is bad, but just abotu tolerable. But the fact that any write to the mode register clears all output lines to 0 (even if the mode register is not in fact changed) is ridiculous. After a hardware reset all port lines are inputs (at least they got that bit right). So a TTL input connected to such a lien will float high, and in any case it's easier to pull a TTL input high than to pull it low. You now program the mode register, and all outputs go low. You cna then set some of them high again. You have to design your peripejhral circuitry to not be bothered by the fact that the inputs to it will be 1 after a reset, and then go to 0 whwen the 8255 is programmed. With better-designed I/O chips (just about all others), you can pre-load the output port regsiters with 1s, then program the driection bits, and the signals to your peripheral logic will remain at 1 parallel port chip until you want to set a p[articular line low. -tony