5 Feb
2003
5 Feb
'03
10:35 a.m.
Ethan Dicks wrote:
Perhaps a little bit of both. If I were going to
emulate a DF-32,
that could be done in battery-backed SRAM - 32K words per unit,
4 units per CPU. Trivial. The original logic was implemented in
R-series logic. It wouldn't be hard to do it all in TTL, just a
bunch of work. The actual storage technology isn't the issue; the
presentation to the PDP-8 is.
Well the most sensable idea is to make the media modular:
bus interface , I/O module , data media.
{snip}
There is a period SCSI card for OMNIBUS PDP-8s - it
has a 6809
processor on it to relieve the PDP-8 of the nitty-gritty details
of how SCSI works. Same idea, slightly newer peripheral hardware.
I think the idea of a processer having about 2000?? transistors
and a 8K core stack, with a i/o card having a cpu with say 68000
transitors and 128kb of memory speaks to me of hardware/software
bloat. ( this does not count the media used even ).
Ben.