TI-99/4A

I always thought the TMS9900 was a neat chip (having a PDP-10 background may have influenced me :-) Having the register set show up in memory gave me a nice warm nostalgic feeling. I wouldn't blame the poor performance of the 99/4A on the CPU. The architecture had a lot of nifty things in it. Most of the blame for the poor performance of the 99/4A falls on the low-end save-every-penny-you-can design criteria for the machine.

I ordered the technical manual on the 99/4A from TI... What I saw in the manual made me gag... aside from a very small amount of memory actually on the system bus, any add-on RAM was accessed _serially_ (i.e. 1 bit at a time) via what TI called a "CRU" interface (basically a high speed serial port) I believe we can all appreciate the crippling effect on any machine's performance when the bulk of it's memory is only available through a 1-bit serial interface. BTW, I also had the technico board... a really neat product that never quite took off. :-( > -----Original Message----- > From: ajp166 [mailto:ajp166@bellatlantic.net] > Sent: Tuesday, January 30, 2001 8:30 AM > To: classiccmp(a)classiccmp.org > Subject: Re: TI-99/4A > > > From: Ross Archer <archer(a)topnow.com> > > > >Correct me if I'm wrong, but I've heard the 99/4A suffered > something of > >an unfair rap for being slow due to the fact that its TI BASIC was > >dreadfully inefficient and sloppy, and that little or no > blame for its > >slowness rested on the actual CPU or hardware. (Windoze > >users may spot a parallel here.) >;) > > Partially correct. there were many issues. One the 9900 is > 16bit wide > data bus demuxed to 8bit (costs a lot of cycles!, penalty 1), > it's run at > less than maximum speed for the time and BASIC {internal} was > interpreted as an end language {penalty 2} and the BASIC interpreter > was interpreted {penalty 3}. > > Those things really hurt speed. The other side was it did have one of > the better from a capability standpoint Basics in the > standard console. > > >The TMS 9900 CPU actually used a "window" in RAM as its > register space, > >with an internal pointer register to locate its base > address. This was > >actually a great idea at the time, because CPU cycles were > long enough > >back then it made no difference whether you stored temporary > values in > >internal registers or external RAM, as either could get you > your data in > >the 1 cycle time available. > > > Actually many of the older DEC hardware also used part fo ram to > implement the registers including early PDP11, DEC-10s and previous > machines. The idea was not new and was to save logic in the CPU > as FlipFlops (memory) were costly in hardware back then and even in > late 70s were costly on silicon. The other factor is the 9900 was > a single chip recreation of the TI990 mini (not unlike like the > 6100{pdp-8}, LSI-11 and DG MicroNova). > > >(And interrupt latency can be really short if you can make a "fresh" > >register bank with one register load!) > > The ability to context switch fast was one of the strong points. > Compared > to Z80 or 8086 it was a nicer cpu to program save for the 32KW memory > limitation. In many respects it was more similar to the minis like > PDP-11 > or Nova than the micros of the time. It was rich in general > registers, > Addressing modes and IO. > > I have a Technico Super starter board and it runs the TI9900 at 4mhz > with 16bit wide memeory and rom really fast compared to the Z80 > (comparison made on both machines I still have from 1979!). > I picked up > the TI99/4a and was sadly disappointed save for the bundle of > really good and inexpensive software for it. Still, it plays > a mean game > of > Parsec!!! > > Allison >