5 Jul
2000
5 Jul
'00
11:03 a.m.
plz see embedded comments below.
Dick
----- Original Message -----
From: Tony Duell <ard(a)p850ug1.demon.co.uk>
To: <classiccmp(a)classiccmp.org>
Sent: Wednesday, July 05, 2000 4:04 PM
Subject: Re: Tim's own version of the Catweasel/Compaticard/whatever
The fact is that you can, but it depends on a number of things including
your definition of properly and the frequency. This circuit is going to be
so slow it won't make a lot of difference for speed reasons. Moreover,
we're talking CPLD, *NOT* FPGA. Routing delays in a sizeable FPGA will have
huge effect on system performance, while those in a relatively small CPLD
like this one are negligible. A CPLD is like a large PAL, AOI-gate-like
architecture with programmable polarity, clock, and either registers or
latches, with various types of outputs. It's not at all like a Xilinx FPGA
of about the same size, e.g. XC3120, andit costs a lot less.
Just a thought about the CPLD vs. TTL discussion: Would it
be possible to design the device such that it could be
built EITHER in TTL chips OR as a CPLD? With the same
I've done a significant amount of design with FPGAs (not CLPDs, though,
so this might be different), and my experience suggests that no matter
what the manufacturers claim you _can't_ take a TTL-based circuit, feed
it into the schematic capture program, and expect the result to work
properly. There are many differences between designing with TTL
and with FPGAs. The
main one is that signals routed across the chip through the various
routing muxes are subject to considerable delays. Delays that can cause
race hazards and glitches where you least expect them. Since the FGPAs
generally have an excessive number of flip-flops anyway, the solution is
obvious -- make everything synchronous. Which is rather different to how
you design with TTL.
By comparison with FPGA's of various types these relatively small CPLD's
are
very easy and pleasant to use. My only complaint is that they never seem to
have the right numbe of pins. Either the package is too big or there aren't
enough pins. <sigh>
CPLDs are a rather different architecture, and probably don't suffer from
this, but it's something to be aware of. Just in case it catches you...
-tony