FPGA VAX update (CDC song)

...or one could use a MIPS chip... To me, the genius (and unrecognized at the time) of the 6600 architecture was Cray's discarding the idea of a "condition code" in the IBM sense, wherein the state of a result is actually divorced from the result itself. The 6600 had no compare instruction, nor condition codes. To compare registers X1 and X2 and branch on the result, one would subtract them and test (via branch) the contents of the result register. Three addresses and no condition codes gave a huge amount of flexibility to placement of instructions in the stream. The 15-bit instruction length for the bulk of instructions didn't hurt either. I recall spending many hours hand-timing loops for the 6600 to get to that magic goal of getting one issue per cycle--and even better if the loop could be fully contained in the "stack" (a 10-word local instruction cache).