18 Dec
2008
18 Dec
'08
10:58 p.m.
That is the real reasion I don't use them ...
times may have changed
but when I looked several years ago all the development kits
did not have a easy way to program the config Proms.
No easy way? It's TOTALLY
hassle-free! With Xilinx, you just have to press a few buttons to compile
and load your design. Works wonderfully!
Many development boards come with USB and Windows software. That's the easiest way. I
use a
JTAG cable under Linux. Works perfectly. I can program the FPGA or the flash.
So everybody
else can do that, too - on an FPGA, of course :-)
I got a CPLD why can't I have the same fun too!
Oddly the only cheap way to program the CPLD's is with CUPL
and all the designs for a VGA display I can't compile easly. > Apropos "main adder": one thing about my
PDP-8 design: It is designed
> for speed, not for size. So there are a lot of
> adders - no adder will get it's input switched. I always have a PC+1,
> PC+2, AC+1, MD+1, etc.
> Results are selected by multiplexers.
The CPU roughly works as follows:
In the first phase, decode, the opcode is already at the output of the RAM.
Memory data is wired to the instruction decoder which makes a lot of tiny signals.
All those signals are registered afterwards. Subsequent cycles in the same instruction
use the registeres variants.
Every register has a source select signal (with own VHDL type *g*) and a load enable
signal.
The state register is always loaded with the "next_state" signal.
All control signals including next_state are made in the combinatorial sequencing process
- it's a
monster!
There exist evil things like pc_next, ac_next etc. They're determined by the selector
multiplexers.
In the last cycle of an operation, load_pc is enabled, memory address source select set to
"pc_next". Then, after the clock, the cpu halts in the decode state or
continues.
On power-on, one fetch cycle is forced, and the CPU halts in decode state as well. With
PC loaded and memory data lines containing the instruction.
ISZ I needs to store the pointer while it does other things with the memory. The MD
register
serves only for that purpose.
A "true" memory data display like in the old machine would need a little bit of
additional logic.
But it's not too difficult to build.
http://hachti.de/download/major_states.pdf
Good design, since you have logic to burn.
Thanks. I HAVE logic to burn... The CPU with much additional stuff like VGA
interface and useless
PS/2 mouse interface currently fills about 60% of a Spartan-3 200K chip. The CPU takes
(estimated,
could have grown) between 20% and 30% of the chip.
Most boards nowadays come with 400K, 500K, 1000K or 1200K gates FPGAs... :-)
So... Why should I keep it small....
Philipp
--
http://www.hachti.de