21 Jul
2016
21 Jul
'16
4:03 p.m.
On 21 July 2016 at 22:22, Peter Corlett <abuse at cabal.org.uk> wrote:
On Wed, Jul 20, 2016 at 09:02:41PM +0200, Liam Proven
wrote:
A load-store architecture is one where the ALU only operates on registers. The
name comes from having separate instructions to load registers from memory, and
store them to memory.
The converse is register-memory, where ALU instructions can work directly on
memory. However, this means that the instructions have to do quite a lot of
work because now data has to be brought in from memory to an anonymous register
to be worked on and then stored back to the same location. This also results in
a proliferation of instruction and addressing mode combinations. Sounds rather
CISCy, doesn't it?
Meanwhile, a load-store architecture would have to decompose that into simpler
independent load, operate, store instructions. Hey presto, RISC!
Thanks for that. It confirms, in a considerably clearer way, what I
had a dim apprehension of.
But load/store automatically RISC? Aren't there non-RISC load/store
processors, and indeed, RISC non-load/store ones?
On 19 July 2016 at 17:04, Peter Corlett <abuse
at cabal.org.uk> wrote:
[...]
RISC
implies a load-store architecture, so that claim is redundant.
Could you expand on
that, please? I think that IKWYM but I'm not sure. [...]
You've already answered the "6502 knockoff" elsethread, so I assume
you're
asking about the predicated instructions.
A predicated instruction is one that does or does not execute based on some
condition. CISC machines generally use condition codes (aka flags), and only
have predicated branch instructions. Branch-not-equal, that kind of things.
In ARM, *all* instructions can be predicated. Because instructions are 32 bits
wide, it has the luxury of allocating four bits to select from one of 16
possible predicates based on the CPU flags. One predicate is "always" so one
can also unconditionally execute instructions.
Aha. Interesting. This I did not know.
If I understand it correctly, this caused considerable problems for
the RISC OS people later. The original Acorn ARM machines used 26 bits
of the program counter as the PC, and the rest as flags. Later ARM
chips do not support this mode, and the OS had to be partially
rewritten for ARMs with a true 32-bit PC -- breaking binary
compatibility with 26-bit code.
I'm not sure this is the same phenomenon you're describing.
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IMO,
it's the predicated instructions that is ARM's special sauce and the
real innovation that gives it a performance boost. Without those, it'd be
just a 32 bit wide 6502 knockoff.
Do tell...?