PDP-8 /e/f/m memory

Allison wrote: Work history doesn't help list readers since they can only read what you've *written* (except for those few clairvoyants sitting in the back row...) :> You neglected to note that Icc grading *between* CMOS static RAMs AT DC varies SUBSTANTIALLY. Power consumption at operating frequency isn't an issue (here). Rather, the difference between Icc(standby) on a "regular" 62256 (e.g.) and a "low power" 62256. For example, a "standard" 62256 can draw ~1mA (1000uA) at standby. A "low power" 62256 can cut that to 100uA. A "super low power" 62256 can cut *that* to 25uA. A factor of 40. You can buy even LARGER devices (e.g. > 1MB -- B not b) that will idle at *2* uA. I.e. the data retention time of a well designed BBSRAM circuit *is* limited to the shelf life of the battery powering it (during standby). *But*, only if you select the right grade SRAM. Note that all three of the *power* grades of 62256 will consume the same amount of power AT OPERATING FREQUENCIES. Roughly 50mA. THAT is a function of clock speed (cycle time). However, the 40 fold variation in Icc(standby) is a different issue entirely. In my reread of your comments, I don't see *that* mentioned. :> (much of the 32KB devices you'll find in PC's and their ilk are not chosen for this very low Icc(standby) -- *especially* cache RAM!) To put things in perspective, a 1F supercap charged *nominally* to 5V (use care here since supercaps typically don't have much margin for overcharge :>) would discharge to 2V (the typical data retention voltage of a CMOS SRAM) in just 3000 *seconds* (less than an hour) with a 1mA retention current. This could be extended to ~30hours using 25uA devices. Using a *2*uA device can extend this to 2.5 weeks... [have I done my math right? Sorry, I'm just doing it in my head so I may slip a decimal or three... :> ] (I am assuming no drops in the switches used to connect the battery to the load. Otherwise, you can lose about 10-20% of the retention time due to drops in the switches).