The HP 9100A/B
calculators use a similar architecture, using
wire bobbins instead of rods, for a microsequence store.
The Wang 500, 600, and 700-series calculators also use a similar
architecture, utilizing "U"-shaped ferrite structures as the
transformer core, for microcode storage.
Now I remember reading an article that mentioned this type of memory.
The article was about radiation-hard memory used on early space
missions.
The described sort of memory is commonly referred to as "core rope
memory" or "wire braid memory", or (in IBM terminology) Transformer Read
Only Store (TROS). The use of such memory in spacecraft computers
(such as the Apollo Guidance Computer) was mostly for the purpose of
saving space and mass compared to read/write core memory, and reliability
in terms of it being nearly impossible to inadvertently (or even
deliberately) change a bit by any means short of gross physical damage.
But the competing memory technology, read/write core memory, was no more
susceptible to corruption by radiation. The cores are physically large
enough that the amount of energy needed to flip them far exceeds anything
they're going to encounter from radiation.
By comparison, in modern semiconductor memory (and RAM-based FPGAs),
single-event upsets are a serious concern, even for ground-based
safety-critical systems. In memory systems, this can be dealt with
by appropriate use of ECC, and possibly scrubbing - periodically reading
the memory and correcting errors often enough that there is negligible
statistical likelyhood of two single-bit errors occuring in the same
word. For FPGAs, there's not a simple solution.
