19 Jan
2007
19 Jan
'07
3:20 a.m.
On Fri, 2007-01-19 02:19:05 -0500, Sean Conner <spc at conman.org> wrote:
I'm currently perusing _Computer Programming and Architecture: The VAX-11_
by Levy and Eckhouse and I come across the description of the CALLG and
CALLS instructions. They go on to describe the stack frame created by the
CALL* instruction:
Condition handler (initially 0) <- FP
SPA | S | 0 | MASK | PSW | 0 FP + 4
Saved AP etc ...
Saved FP
Saved PC
Saved R0
.
.
.
Saved R11
My question is about the condition handler. In the text, it's described
as:
A longword condition handler address. Here, the calling routine
may store the address of an error-handling routine to be called if
an exceptional error condition arises in the procedure.
The _VAX Architecture Reference Manual_ (ISBN 0-932376-86-X, DEC
Order-No. EY-3459E-DP) handles this a little better, but doesn't
explain it's real-world usage as well:
In order to preserve the state, the CALL instructions form a
structure on the stack termed a call frame or stack frame,
shown in Figure 3.2. This structure contains the saved
registers, the saved PSW, the register save mask, and several
control bits. The frame also includes a longword that the CALL
instructions clear; this is used to implement the VAX/VMS
condition-handling facility. Refer to the /VAX/VMS Run Time
Library Reference Manual/. At the end of execution of the CALL
instruction, FP contains the address of the stack frame. The
RET instruction uses the contents of FP to find the stack
frame and restore state. The condition-handling facility
assumes that FP always points to the stack frame. Note that
the saved condition codes and the saved trace enable (PSW<T>)
are cleared.
Figure 3.2 (showing the stack frame's organization) is similar to
yours, but (FP + 4) is different:
SPA | S | mask<11:0> | Z | saved PSW<14:5> | 0
with Z described as "Always cleared by CALL. Can be set by software to
force a reserved operand fault on a RET."
This is the only section (as far as I can tell)
where this is described,
and I'm curious as to how exactly it worked. It appears that while the CPU
may set this location to 0, its purpose isn't really dictated by the
hardware, but it a convention used by VMS. But then (as I was typing this),
I was struct by this bit:
I googled for it and this
(http://www.math-cs.gordon.edu/courses/cs222/lectures/exceptions.html)
showed up. It makes sense, but it's not authoritative :)
MfG, JBG
--
Jan-Benedict Glaw jbglaw at lug-owl.de +49-172-7608481
Signature of: Gib Dein Bestes. Dann ?bertriff Dich selbst!
the second :