10 Apr
2007
10 Apr
'07
4:19 a.m.
Christian Corti wrote:
/RDDAT is the data the floppy drive fed out.
DATA is the bitstream after the data separator has cleaned it up (it sometimes
double-clocks, but that doesn't seem to matter).
DWIN is the Data Window. When it transitions from high-to-low or low-to-high,
a new data or clock cell starts. If there's a transition on DATA during the
cell, then the bit is a 1, else it's a 0. Clock and data bits are mixed
together, but based on the SYNC state, you can figure out what phase of DWIN
signifies a data bit.
Stupid question: where is the PLL? Is this a digital
PLL built around
the SN74188? Isn't that only the data separator, i.e. detection of data
windows, which is then MFM only? This design looks a bit too primitive...
It's a state machine.
[...]/hpla-fdd-reader-syncing-against-720k-floppy-zoomed-long.png
Hmm, /RDDAT, DWIN and DATA don't look right to me. You seem to generate
DATA bits during clock time. Is /RDDAT coming from the floppy and is
DATA going to the FDC? /RDDAT shows the bit pattern 10100001, i.e. $A1. But
the address mark
for MFM consists of four bytes ($A1A1A1xx), and the address mark bytes
have clock bits 2, 3 and 4 removed, your data stream seems only to have
bit 3 removed.
Um, no.
The MFM sync word does decode as 0xA1, but it has a missing clock bit in the
lower nibble - it's encoded as:
01 00 01 00 10 00 10 01
^
missing clock
Which is invalid MFM data, but still maintains the (1,3) RLL property, so the
drive and data separator aren't confused by it.
Take into account that you're looking at a waveform with the SYNC output
skewed by one DWIN transition. The first '0' is missing from that trace. DWIN
changes state just before the X marker, clocking in a 0.
Then DWIN transitions again, and because there was a transition on DATA in
that bit cell, a 1 is clocked into the shift register. So now
SR = xxxx xxxx xxxx xx01
Skip ahead to the next DATA pulse - DWIN has changed state three times,
clocking in three zeroes. So SR = xxxx xxxx xx01 000. Then DWIN changes state
again, and because of the DATA pulse, a 1 is clocked in. Now
SR = xxxx xxxx xx01 0001.
Now skip ahead to the DWIN=1 before the second sync pulse. Now
SR = x010 0010 0100 0100
DWIN changes state again, clocking the 1 into the shift register. Now
SR = 0100 0100 1000 1001
SR is equal to the sync word, so the SYNC output goes high. In the 'early'
version, this was a registered output timed against DWIN, so it lagged by one
DWIN transition. In the new version, it's a combinatorial output (a straight
compare).
Does that make it any clearer?
Thanks.
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