20 Jun
2007
20 Jun
'07
10:44 p.m.
Subject: Re: T11 design WAS - Re: Inside old games machines,was: Re: Simulated CP/M-68K?
From: "Ethan Dicks" <ethan.dicks at gmail.com>
Date: Wed, 20 Jun 2007 16:22:25 -0400
To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at
classiccmp.org>
On 6/20/07, Roger Ivie <rivie at ridgenet.net> wrote:
It's part of the memory to memory design and the way intructions work.
It's annying as micros go but ALL PDP-11s word that way and the T-11
is a PDP-11 in LSI.
On Wed, 20 Jun 2007, Allison wrote:
> It's an easy cpu to interface and use...
However, it's not without its obnoxious bits.
On the T-11, all writes are performed as read-modify-writes.
Hmm... was that because of the needs of core memory, or was it just to
simplify some aspect of its internal design? RMW cycles are typically no problem with main memory,
but I've seen
problems with them in a number of situations involving I/O, typically
involving "clever" peripherals that take a read of some register as a
trigger signal, but also with some 68000-family designs where you
weren't allowed to use instructions in your code which invoked RMW
cycles because they weren't interruptible (intentionally) and could
cause interrupt or instruction-restart problems.
Yep the fix is easy. The read address is dirrent from the write address.
So when the system doe sthe read before write or Read modify write
it only touches the address register for thatread or write as desired.
At least with the 68000, RMW cycles were rarely done by
real-world
code, and never accidentally.
With a from-scratch T-11 SBC, one could, I'd expect, select I/O
peripherals that wouldn't be subject to side-effects (like clearing
status bits on reads), but that's a lot harder when you have a mandate
to use a particular vendor's chip and the chip tries to be clever.
Easy, make the read and write different addresses. Just like PDP-11s do.
Allison