4 Jul
2000
4 Jul
'00
1:34 p.m.
At 06:11 PM 7/4/00 -0700, someone wrote:
Not all FPGAs use RAM, infact it is one of the suggested advantages of
Xilinx FPGAs but it isn't a requirement. CPLDs generally have simpler
configuration blocks (or macrocells, or what ever the manufacturer wants to
call them)
The CPLD
offers a number of advantages over FPGA's. They're not the same.
An FPGA uses a RAM lookup table in to define the function executed by a
logic cell. CPLD's use EPROM/EEPROM cells to store the logic
configuration.
> Most FPGA's require an external configuration prom of one sort or another,
> which it boots on reset. Actually it's pretty easy to get an Xylinx FPGA to
read a program from a
serial or parallel line, so all you need to do to reprogram is assert reset
and feed in the data correctly.
This is true and the ultimate "catweasal" type board would have a nice fat
ram loaded FPGA connected to the interface logic and a high speed ram
buffer. Probably a programmable clock too. That way you could run anything
from an actual WD1793 type chip to an HP logic analyzer
just by downloading
a different setup.
--Chuck