RFC: Floppy reader/writer project

Hi guys, The USB floppy reader project is back on track as of about an hour ago. I've found a distributor who has a couple of Altera FPGAs in stock, and although it'll take a few days for them to arrive from Belgium, they were quite happy to sell me just five of them. For anyone that wants to look up the datasheet, they're Altera Cyclone II devices, p/n EP2C8T144C8N. Cost was ?11.58 +VAT. This nifty device also has a pair of onboard PLLs - which means I can put a relatively low-speed oscillator on the board, then boost the clock up to whatever the acquisition clock needs to be, and generate the 32MHz clock for the data separator / sync detector with the second PLL. Very cool. A quick does-this-work-or-not test build of the code I was using on the Xilinx chip clocked in at 5% utilisation of the Cyclone -- that means the final version will more than likely use a smaller chip (likely an EP2C5; the entry-level Cyclone 2). I'm still using the "time the length of the time between RD_DATA pulses" method for acquiring the data, but I'm increasing the acquisition clock so that the reader can measure the timing down to an accuracy of 50ns minimum (25ns with the 40MHz clock option). The counter is now 15-bit with an INDEX (index pulse was high at data bit leading edge) bit for every counter word. This gives a maximum counter period of 1.6384ms at 50ns, or 0.8192ms at 25ns... or a minimum bit rate of 610 or 1220 bits per second respectively. Maximum data rate is likely to be around 5-10Mbps. From what I've been told, the Trace disc duplicators had an accuracy of 50ns, which is where the base clock for the floppy reader came from (the SPS have based most of their data analysis on Trace duplicators, so the clock rates need to be close-or-identical). I've also scrapped the SRAM storage in favour of SDRAM. For the ?5 unit cost of the 256K*16 Cypress SRAM, I've managed to get a 4M*16 PC133 SDRAM chip. This gives a maximum track length of 4*1024*1024 (4194304) magnetic transitions; probably far more than any floppy disc ever made. Like I said before - the aim isn't to get an image with the intent of only decoding it (although the hardware can be rigged to do that). The aim is to be able to get as much information off a disc to be able to state that: - The data is accurate - The data is original (timing will differ between two drives -- if e.g. a high score table has been modified on a factory-written disc, the modification will be at a very slightly different data rate). Also, if you've only got one chance at reading a potentially-defective disc, you want to get as much information from that disc as you possibly can in the time you have. This is what I consider to be the spec at this moment in time: CPU: Microchip PIC18F4550 USB MCU at 40MHz (10MIPS peak) with Altera FPGA coprocessor / DAQ controller RAM: Micron Technology 4M*16 SDRAM Interfacing: USB Full Speed (12Mbps), RS232 as a jumper selectable option (115200 baud). Power: 5V DC from USB port, external supply required for drives Features: - Open-collector outputs, high-voltage (30V) tolerant - Over-voltage protected TTL level inputs with pull up resistors - Standard 34-pin drive interface, with 6 User I/O pins - Acquisition start/stop methods: - Both leading and trailing edge event triggers available (trigger-at and trigger-after) - Event Counters for all events -- wait for event to occur N times before triggering - Instant On (starts as soon as START bit is set, not valid for STOP) - Stops when memory full (always enabled) - MFM Sync word detector -- detects a 16-bit MFM word (e.g. Sync A1) - Index pulse -- typically start on leading edge, stop on trailing - Hard-sector track mark detector -- detects the double-pulse track marker and triggers from the index line - Fully reprogrammable -- boot-block protected Flash on PIC, 8Mbit Atmel DataFlash to configure FPGA. - Two user-selectable FPGA microcode blocks -- store standard FPGA code in one half of the DataFlash, and customised code in the other. - Fully open-sourced design -- hardware, software and HDL code -- basically under the "Wisp628 licence": - The design is open, so you can tweak, modify and play with it as you see fit - What you aren't allowed to do is sell kits, or pre-built units for profit. So if someone asks you to build one for them from scratch (i.e. not used to build it. - Software is GPL2 without the "or any later version" clause, plain and simple. So the inevitable questions from me: - Am I too late with this? Is it worth continuing and finishing the project? - If I said one of these boxes would cost ?75 (around the same as a Catweasel), would you buy one? - Are there any features you guys think I should add? - Does the licence sound too restrictive? I've put around ?300 into the project thus far, not counting time. I know I've got basically no chance of recouping all of it, but it would be nice to make at least some of that money back. Like the subject line says - this is a Request For Comments - I know I'm not going to please everyone, but I'd like to get as close as I can :) I've set up a mailing list at <http://mail.philpem.me.uk/mailman/listinfo/floppy-reader_philpem.me.uk> to carry announcements and discussions about the project -- saves cluttering up classiccmp with it (unless people would rather discuss it here?) Thanks, -- Phil. | (\_/) This is Bunny. Copy and paste Bunny classiccmp at philpem.me.uk | (='.'=) into your signature to help him gain http://www.philpem.me.uk/ | (")_(") world domination.