18 Oct
2004
18 Oct
'04
1:55 p.m.
The PC approach is to somehow wangle the five ADCs into the PC
such that it will accept the 65536 5-byte (5-nybble) samples
with ZERO LATENCY.
--
The design I did for the analog 9 track data aquisition board
uses five Analog Devices 10 bit dual 10megasample A/D's. These
have parallel outs, and are synchronous (designed for direct
IF amplifier digitization). The five are multiplexed into a
FIFO which interfaces to a 40 pin cable to a PCI DMA IDE card.
So, you end up with a ten channel synchronous data stream with
a protocol that just looks like chained IDE DMAs.