Tim's own version of the Catweasel/Compaticard/whatever

The CPLD offers a number of advantages over FPGA's. They're not the same. An FPGA uses a RAM lookup table in to define the function executed by a logic cell. CPLD's use EPROM/EEPROM cells to store the logic configuration. Most FPGA's require an external configuration prom of one sort or another, which it boots on reset. The FPGA has lots of logic available, though it's uncommon for more than half of it to be useable. CPLD's have less logic, but it's all available and often used up. Having several devices on the same footprint with differing capacities is very useful, since you can then save money by using a device that's "barely" enough without changing device packages. Neither of these technologies offers enough drive to handle a FD cable, however. It's remarkable how little logic is needed to do a job like this one. Aside even at 32x that it easily allows writing a byte to the RAM in or reading a cheap and ubiquitous part to use is a 1Mx4 DRAM. The addresses can be muxed in the CPLD and refresh (while it's idling) is easy to in hidden mode, in which it uses an internal refresh counter. I don't know what 256Kx8 SRAMS cost these days (I could look ...) but if I already have 1Mx4 DRAMS, it's easy to choose. The data port on the RAMs can be handled with a single serial/parallel in, serial/parallel out shift register (like a 74195) that allows you to operate on the data interface with the RAM each 4 bits by either loading or reading the shift register. I like this CPLD approach because anybody who wants to try their hand at this can do so at no cost other than materials because the software is available over the web, the programming cable schematic is available at www.xilinx.com, and the software with which to program the things is also on the web. The cable is even useable with other manufacturers' devices because it is virtually standardized. My download cable is made such that I can switch pins from one header to another so I don't have to have two cables, one for XILINX and one for everyone else. It's not an expensive arrangement, however. As I wrote previously, the software also provides a really handy way to communicate schematics between folks working with the same software. I've not seen Tim's logic diagram for his sampler, but I do have one of my own, and find that there's not enough logic involved to warrant use of a CPLD in mine. It consists of a PAL, two counters, two shift registers and a couple of 256Kx4 DRAMs. These components were chosen because I had them, not because they lead to an elegant design. The entire sampling circuit will easily fit into the small CPLD that's been suggested, including the DRAM interface, and the interface to the PC's EPP port. If this thing is to function as a rudimentary FDC, which would be VERY convenient, then it would be easy enough to limit the current on the cable by keeping it short and substituting larger resistor values for the 150-ohm numbers found on many drives. That will solve the drive problem and shorter cables will not mind. I'd encourage everybody to try it. These in-circuit programmables are really neat! I like 'em LOTS better than FPGA's, though there are getting to be a number of in-circuit programmable config proms as well. Dick ----- Original Message ----- From: Eric J. Korpela <korpela(a)ellie.ssl.berkeley.edu> To: <classiccmp(a)classiccmp.org> Sent: Tuesday, July 04, 2000 1:51 PM Subject: Re: Tim's own version of the Catweasel/Compaticard/whatever send these advantage that