Accelerator boards - no future? Bad business?

On Sat, 23 Apr 2016, Sean Conner wrote: Pipeline restrictions were gradually relaxed by adding more and more interlocks as the architecture evolved. So while user mode code compiled for a higher ISA might not necessarily work with an older one even if it only used instructions defined in the older ISA, there was no issue the other way round, old code was forward compatible with newer hardware (or, depending on how you look at it new hardware was backward compatible with older code). The timeline was roughly: - MIPS II -- removed load delay slots -- for memory read instructions targetting both general purpose and coprocessor registers, - MIPS IV -- removed coprocessor transfer and condition code delay slots -- for instructions used to move data between general purpose and coprocessor registers as well as ones setting or reading coprocessor condition codes. The original MIPS I ISA only had an interlock on multiply-divide unit (MDU) accumulator accesses, so all the other pipeline hazards had to be handled in software, by inserting the right number of instructions between the producer and the consumer of data; NOPs were used where no useful instructions could be scheduled. Some operations continued to require a manual resolution of pipeline hazards even in the MIPS IV ISA, like moves to the MDU accumulator, as well as many privileged operations (TLB writes, mode switches, etc.). For these the SSNOP (superscalar NOP) instruction was introduced, which was guaranteed not to be nullified with superscalar pipelines. The encoding was chosen such that it was backwards compatible, using one of the already existing ways to express an operation with no visible effects other than incrementing the PC, which given the design of the MIPS instruction set there has been always a plethora of. Consequently SSNOP was executed as an ordinary NOP by older ISA implementations. NB despite the hardware interlocks it has always been preferable to avoid pipeline stalls triggered by them by scheduling the right minimum number of instructions between data producers and the respective consumers anyway and compilers have had options to adapt here to specific processor implementations. The addition of hardware interlocks made the life of compiler (and handcoded assembly) writers a little bit easier as a missed optimisation didn't result in broken code. Also more compact code could be produced where there was no way to schedule useful code to satisfy pipeline hazards and NOP would have to be inserted otherwise. I won't dive into the details of the further evolution with modern MIPS ISAs here, for obvious reasons. Maciej