12 Jun
2010
12 Jun
'10
5:55 a.m.
On Fri, 11 Jun 2010, Sridhar Ayengar wrote:
Chuck Guzis wrote:
As I metioned in a response to the original post, all A2 accelerators that
I'm aware of slow to 1Mhz. for GCR floppy access.
The only exception might be the internal logic for the original Unidisk
3.5" drive. It used an embedded 65C02 and could read entire tracks at a
time. However, it relied on very conservative 4:1 physical sector
skewing.
For the IIGS, Apple developed a custom ASIC for diskette I/O that I
believe could operate at a 2Mhz. clock. With the newer "dumb" 3.5" Apple
drives, it was capable of reading track-at-a-time with 2:1 interleave.
The fun started when you read such a diskette on a Unidisk 3.5 :-) It got
2x slower than usual due to an extra rotation between every sector
transfer. Even on the IIGS, accelerator cards slowed to the "as designed"
clock speed for diskette I/O.
Steve
--
I suppose "good enough" accurately
describes the Apple II scheme;
"gutless wonder" would be another term that comes to mind. GCR with
the only error conrol being a one-byte arithmetic checksum on each
sector. Were there ever any "turbo" mods to run an Apple II at more
than 2MHz without breaking the floppy logic?
I don't know about the ][ itself, but the ZipChip accelerator for the //c
runs at 4MHz with the floppy operating correctly.