On 06/11/2010 02:12 PM, Chuck Guzis wrote:
I think later controllers (as used in the 5170) used
the
all-digital WD9216 type of data seaparator.
The SMC 9216 and 9229 (and the Western
Digital second-source) are
actually quite good. They use a DPLL. The 9239 uses an even better DPLL.
With the all-in-one FDCs
(WD37C65, N82077), the question of data separator design became a
nonstarter. Just plug it in with no adjustments needed.
Some of the all-in-ones used an analog PLL (notably the 279x), some a
DPLL. I've never had any trouble with them, so I think they're probably
designed reasonably well.
I suppose "good enough" accurately describes
the Apple II scheme;
"gutless wonder" would be another term that comes to mind.
I would argue
that it's some of the best engineering ever, bearing in
mind that all engineering involves tradeoffs. (I would argue that the
essence of engineering is knowing how to make the tradeoff of getting
the best design for the constraints, including the manufacturing cost.)
The GCR is being done at effectively the single-density flux-transition
timing, so doing a simple state-machine data separator (which is better
than a one-shot but not as good as a PLL) is actually adequate.
GCR with
the only error conrol being a one-byte arithmetic checksum on each
sector.
For a small sector size, a one-byte checksum isn't that bad.
Were there ever any "turbo" mods to run
an Apple II at more
than 2MHz without breaking the floppy logic?
No. You can't even run at 2 MHz. The accelerators all slow down to
normal Apple II speed (effectively 1.023 MHz average) for disk access.
The final disk controller Apple offered for the Apple II, the one that
could handle the high-density 3.5" "Apple Superdrive" (not to be
confused with their later DVD "Superdrive"), used an on-board 6502 core,
running at 2 MHz IIRC.
Eric