Front panel switches - what did they do?

On Tue, May 24, 2016 at 3:09 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote: That's a great write-up! Thanks! I'm not sure about how IBM TROS was driven, but the core-rope memory I've examined was not from an AGC and didn't use the switching core technique, so I wouldn't consider that decode technique to be an inherent property of core rope memory, although it's certainly clever. The core rope memory I examined had 64 words. Of the six address lines, three fed a three-to-eight decoder with high-side drivers, and the other three fed a three-to-eight decoder with low-side drivers. Each of the 64 word drive lines was wired between a unqiue pair of high-side and low-side drivers. That required significantly less circuitry than a single-ended six-to-64 decoder. The same technique was used for the X drive and Y drive of "normal" core memory, such as the PDP-1 drivers for the Fabritek 4K planes in the PDP-1 at CHM. (There was an earlier model of PDP-1 core memory that might have used a different drive scheme.) The X drive used one pair of eight each high and low side drivers, and the Y drive used another such pair.