Homebuilt TTL and transistor CPUs - wierd logic

All, way behind on my digests, sorry for the time-warped reply. At 12:00 -0600 1/5/06, Chuck wrote: ...and my nomination for hobbyist research is: Balanced trinary! (Possibly using superconductors and SQUID detectors.) Balanced trinary means place values go up by three each, but instead of each place containing symbols worth 0, 1, or 2 times the correct power of 3, the symbols are worth (-1), 0, or 1 times that power. Using the letter n for the (-1) symbol, a short counting table is: BT Decimal ... nn -4 n0 -3 n1 -2 0n -1 00 0 01 1 1n 2 10 3 11 4 1nn 5 1n0 6 1n1 7 10n 8 100 9 101 10 ... No need for a negative sign bit, it's built in. Each memory cell needs to hold 3 states, which for superconducting loops should be clockwise, no, or counterclockwise current. Of course, you could simulate this using 2 binary gates to carry each trinary digit - thus wasting 25% of the practical power of your computer (compared to implementing it as base-4). But if Moore's law holds up, that'll only set you back about 3 months compared to conventional binary computers.... Hope at least some of you are laughing by now. Practical applications *do* exist. You can get a long way with just a few weights (one each power of 3) and a balance scale using this system, for example. "n" weights go on the platform with whatever's being weighed, "1" weights go on the other side. -- - Mark 210-522-6025, temporary cell 240-375-2995