12 Nov
2005
12 Nov
'05
6:04 p.m.
On 11/12/2005 at 10:49 AM woodelf wrote:
This is making me think twice to goto LS. Now what I
need help is with
the J/K flip flops (TTL).
7473 -- "Do not change J/K while the clock is high." But I want to
STOBE J/K when the clock is
high for a D F/F. Will this work in practice?
According to my databooks, "The J and K inputs must be stable one setup
time prior to the HIGH-to-LOW clock transition for predictable operation".
So, yes, you can change J and K while the clock is high--you just have to
build in some settling time. My databook says this is 0 ns for the TTL
part and 20 ns for the LSTTL part.
Why not use 107's? Better output drive and "corner" power connections.
Cheers,
Chuck