DEC bus transceivers

On 10/25/2016 04:24 PM, Guy Sotomayor Jr wrote: Its not. It may be close but.... What your reading is the terminator value (R1+R2)/R1*R2=120. thats a terminator and its also limited in the range of values because the DEC part can only sink so much and also the terminator has to source current as the driver can't. Likely the line impedance can be in the range of 120 ohms, maybe. I"ll have to drag out a Qbus back-plane and measure it. I don't have any Unibus. As far as the chips themselves. They do NOT match the line impedance as they have a active low value in the 10 ohm range and when in the high state they are just an open or somewhere in the effectively infinite range certainly more than several thousand ohms. That's a terrible mismatch for transmission lines, aka bus. The combination of wacky source impedances and near open load impedance (input current varies with source voltage Vih and Vil) plus parallel capacitance from package and traces on board means that as a load its a horrid mismatch as well. With all that reflections (ringing) are to be expected and the only thing that can help that is the terminator even then only to a point. In short most TTL are no better and those designed to do bus interface are about the same. Also CMOS would be far worse as a receiver and some CMOS makes a better transmitter but they are incompatible with Unibus/Qbus as they actively source current. The only common tech that does line matching especially from that era is ECL, or current mode logic. This is why faster buses are so difficult to make right. And if possible they are to be avoided or made small as possible. Been there and done that,, mixed signal design for the last 40 years. Allison