9 Aug
2009
9 Aug
'09
6:06 p.m.
On Mon, 10 Aug 2009, Johnny Billquist wrote:
Roger Ivie <rivie at ridgenet.net> wrote:
Second, the vector transfer isn't a normal bus transfer in the sense of the
device addressing the CPU and transferring a word.
Page 2-13 of the UNIBUS spec (1979): "INTR is a bus signal asserted by
an interrupting device *after it becomes bus master* to inform the
interrupt fielding processor that an interrupt is to be performed and
that the interrupt vector is present on the D lines."
Technically, you don't even have an interrupt until the device hands you
the vector. Which it does as a bus master.
The CPU cannot be a slave,
unless my memory fails me.
Page 2-14: "INTR is negated upon receipt of the assertion of SSYN from
the interrupt fielding processor."
It's been way many years since I looked at the
unibus map of the VAX UBA, but
I can't for my life imagine that it could be any simpler than the Unibus map
of the PDP-11.
The PDP-11 can map a UNIBUS page to any *word boundary* in the memory
space. That means there are adders in there somewhere. The VAX
scatter/gather map just replaces bits 9 and up with the contents of the
map entry.
--
roger ivie
rivie at ridgenet.net