16 Apr
2007
16 Apr
'07
3:47 p.m.
Jules Richardson wrote:
hacking time...
Is parity generation a simple case of chaining exclusive-or gates for
the required number of data bits? e.g. for 8 data lines:
d0 --+
XOR--+
d1 --+ |
XOR--+
d2 --+ | |
XOR--+ |
d3 --+ |
XOR--- parity
d4 --+ |
XOR--+ |
d5 --+ | |
XOR--+
d6 --+ |
XOR--+
d7 --+
(possibly inverted at the end, depending on requirement for odd/even
parity)
... I think that works, but thought I'd ask for list wisdom first :) I
don't have a parity generator IC (LS280?) handy, but if the above works
then a couple of LS86 chips would do the job*.
*possibly a little slower than a "proper" LS280, but that's not critical
for what I had in mind.
cheers
Jules
Jules, your understanding is absolutely correct.