12 Nov
2008
12 Nov
'08
11:50 a.m.
dwight elvey wrote:
Although, not described in most books on cores, the
inhibit lines
were quite common. The use made it so that there was greater
margine between the signal level of the address line running through
the row or column bit that were not addressed and the one
bit the that was to be read or written.
Perhaps that was the purpose in some core systems, though I've never
heard of it. In the core systems with which I'm acquainted, the inhibit
line is used to inhibit writing to the otherwise-selected core in one
plane. Each plane in a stack is used for a single bit of the parallel
data word. For instance, a 4Kx12 stack would have twelve planes each
organized as 64x64. The same X-Y decode and drive is used for all
twelve planes, so in order to write a data word having ones in some bit
positions and zeros in others, the inhibit lines for planes
corresponding to the ones are active (or vice versa, depending on the
system).
In very early core stacks, there were separate wires for sense and
inhibit, so there were four wires through each core. It wasn't long
before they started using the same wire for both sense and inhibit.
http://www.cs.ubc.ca/~hilpert/e/coremem/index.html#3wire
Eric