On Mon, 20 Jun 2016, Paul Koning wrote:
  used to how C or similar languages work.  For example,
in this C code:
        a = 1;
        b = a;
 a and b will both equal 1 at the end.  But in the VHDL code:
        a <= 1;
        b <= a; 
Whoa. That makes total sense, though. In the real world, I'm guessing the
"less than" just reflects that a signal might not have the level you
expect.
  But it fits hardware, where signals have to propagate
and new things
 happen as a result of previous actions at previous points in time. 
It makes me wonder what kind of person had to figure out all those effects
and enshrine them in a deterministic language. That sounds very
challenging. Hats off to them.
  VHDL and Verilog can be used to model hardware
operation; they can also
 be used to describe hardware.  These are not quite the same. 
I've got a tab in my browser with an article about the differences. I like
strongly typed languages, so I'd probably start with VHDL if I can get
that far.
  A model can, for example, talk about actual delays.  A
hardware
 description does not; such a "synthesizable" model is a subset of the
 full language. 
Ah, okay. I had wondered what that meant when Ian had mentioned it.
  This is a common way to design what goes into an FPGA.
A hardware model
 can be used to replicate what old hardware did; for example, I have a
 partial CDC 6600 model that shows how it boots, and that model includes
 propagation delays on some signals (which are critical to correct
 operation in certain spots). 
Wow. All I can say is "I wish I could do something like that, too." :-)
  For example, if all you have is a complex IC spec
sheet, it is likely to
 be rather difficult.  If you have internals, it becomes more feasible. 
Hehe, I keep up this page a lot: 
https://www.sparkfun.com/tutorials/223
 It's concerning how to read spec sheets.
... because reading these sheets is about like reading a man page for
non-UNIX users, it's tough at first, but then becomes very valuable!
  There are plenty of textbooks on the topic.  I would
recommend the
 (large) book by Peter Ashenden on VHDL.  He also has a book on Verilog;
 given how he treated VHDL I expect that one is good too but I don't have
 it. 
I'm not there yet, but I've bookmarked a copy at Half-Price Books and I'll
come back to it if I make it through my digital logic course with brain
cells to spare.
-Swift
PS: Thanks to you and Ian for the nice explanations and answers.