31 Dec
2008
31 Dec
'08
6:14 p.m.
Guy Sotomayor <ggs at shiresoft.com> wrote:
The problem with replacing the cache is that it is composed of 4 hex
boards (M8142, M8143, M8144 and M8145). I haven't looked at the
backplane signals, but I'm dubious that it could be done with less.
Correct. The cache and memory controller is a total of four cards.
But unless my memory fails me, all the signals needed are actually
located in just two of the slots. So you'd have to go with a two card
solution. Either one card and paddles, or two cards with interconnects.
On Dec 31, 2008, at 8:16 AM, Ethan Dicks wrote:
>> Skip the memory bus and the original cache. The original cache is
>> just 2 KB
>> of 2-way associative memory. If you set up a 4 MB cache, the CPU
>> can run at
>> full steam the whole time, with a cycle time of about 150 nS, if I
>> remember
>> right.
> Handy, since 70ns SRAM is easy to find.
True. And 70ns is definitely fast enough.
It is more complicated, though. You'll have access
paths from CPU,
Unibus
and four massbus controllers to deal with. But it should definitely
be
doable (heck, SETASI have already done it once).
I might be interested in such a project myself, since the 11/70s we
have
around here still are on MK11 boxes. I could deal with PCBs and
design, but
I'm very short on time, as usual... :-(
No experience at all with FPGAs or any such fancy stuff.
If such a thing were to
be designed (I could participate in the design
phase, but not drive it), I'd probably be interested in two,
especially if the blank board was only a few hundred dollars. If it
came closer to $1000, I'd really have to think about passing on the
second one (I used to order multi-layer DEC backplane boards, and at
the time, $500 was a good price for orders between q10 and q100, but
things in the PCB market have changed radically).
I'm in no hurry - my 11/70s are in storage and I won't be able to even
pull them out to look at them in the next 90 days. The advantage of just replacing the MK11 boxes, is
that it could be
done with just one board. Depending upon signaling and such (and with
sufficient integration - ie FPGAs and SMTs) it *might* even fit on a
quad board vs hex.
Oh, it could definitely be done with just one quad board. The memory bus
is really simple.
It's just that you won't get much of a speed gain that way, so it will
mostly be a space and power save thing.
Not at all as interesting, atleast not from my point of view.
You can probably get it all in with through holes on a quad card even.
The memory bus is really simple to interface. And since you'll keep it
in the CPU box, and have the full 4 megs on one card, you can ignore all
the requirements of the bus drivers for the memory bus as well.
The 11/70 memory bus is otherwise designed for quite a long signal path.
Total max was two cabinets full of memory boxes, or eight of them. That
would get it close to ten feet. Power was accordingly.
So, while not Unibus, there are drivers and terminators on that bus as
well. (Actually, the terminators are the same as those small cards that
terminate a massbus, if anyone ever disassembled one of those.)
Remember, SETASI did this on a hex card something like 20 years ago, if
not more. Most of the area was probably memory chips, which can be
reduced extremely much by now.
But, as I said, I don't find that exercise very interesting.
The other issue with not replacing the cache, is that
the verilog to
implement this would *much* simpler (ie it can probably be completed
faster).
True. Simple stuff is always faster to actually do. :-)
And to make a few comments on other stuff that's been mentioned.
You don't seem to appreciate the speed of things on the memory bus. A
read cycle form the MK11 was typically something like 600ns, and could
be as much as 1200ns (when error correction was required), if I remember
right. Write was just as bad, while modify was worse. The max speed
possible is still much lower than 150 ns, which is what the CPU will run
at when you have cache hits (assuming my memory is right). There is
setups, handshakes and signal propagations on a big bus involved.
70ns memory will definitely be sufficient for whatever we would design.
Surface mount or through? Well, I don't really have much of a
preference. Of course, through hole is easier to solder, test and
repair, but they do take more space. And I can do either.
My cad program have extensive libraries for all of it, so that's not a
problem.
I very much doubt that we'd have any problems getting it all into one or
two cards.
One advantage of replacing the cache is that then we'd definitely just
talk TTL. No buses with drivers at all.
Much simpler and cheaper from that point of view.
Absolutely best would of course be if we could find drawings for the
HC-70/PEP-70 combination, and use those as the basis for a design, and
just improve by using current available technology.
But of course, since I'm not offering to do this, except as a spare time
project to aid in a community effort (unless I could actually make up
for the time I would spend on it, and I somehow doubt there is a
commercial case for this nowadays). So if anyone else wants to design a
memory card to hook to the 11/70 memory bus, I definitely won't stop
them, and might try to atleast give some helpful comments.
Johnny