8 Feb
2003
8 Feb
'03
5:08 a.m.
On Feb 8, 11:06, Jim Keohane wrote:
The reference to "one cycle" instruction may
have been referring
to there being 2 cpu cycles per clock cycle. Also, there's the
"pipelining"
some say the 6502 does when the last (or only) byte of
an instruction
is
acted upon simultaneous to next instruction's 1st
byte (opcode) being
fetched
So perhaps "one instruction per clock cycle" may be awfully close
with
pipelining and with use of zero page.
You must be thinking of some different 6502 to the rest of us :-) As
Sellam said, no 6502 opcode takes less than two clock cycles to
execute, and most take more (up to 7): the only 2-cycle instructions
are the ones with implied addressing, like RTS, CLI, TAX, ... This is
why a 6502 running typical well-written code, running on a 2MHz clock,
manages at best around 0.7 MIPS.
There's no pipelining at all in a 6502. No overlap of instructions
whatsoever.
Zero-page instructions like LDA $12 take three clock cycles.
There aren't two CPU cycles per clock cycle. Perhaps you're thinking
of the fact that the 6502 uses a two-phase clock, and does part of the
CPU cycle during phi-1, and part during phi-2?
Of course, we're talking Apple ]['s which,
if I can trust my
memory,
steal every other clock cycle to refresh memory.
I believe you're thinking of how it uses part of the clock cycle when
the CPU isn't accessing memory, not alternate clock cycles.
> > p.s. I also did quite well with 6502 asm
code in cpu speed tests
vs
> > 80x86 and Z80 programmers. The zero page,
for all intents and
purposes,
> > is 256 registers.
That was the designers' intention, but you have to remember that it
takes an extra clock cycle to access a zero-page location rather than a
register.
--
Pete Peter Turnbull
Network Manager
University of York