18 Dec
2008
18 Dec
'08
10:38 p.m.
Hi Vince,
I know. But there's no
open collector logic in an FPGA (as I know).
:-)
Nice. I like it, too :-)
Using Xemacs' VHDL mode.
I'm hoping to get around that by declaring TP1...TP4 (and *strobe*, etc.)
to be the clocks, and re-expressing the latches so that they are clocked
by an "official" clock. I don't know yet how well that is working out,
as it's buried in with the other 188 warnings-of-the-moment.
That still sounds **EVIL** !
FPGAs are made for fully synchronous designs with only a single clock (or with a few clock
domnains,
of course).
What you are doing is using LOTS of gated clocks. The tools don't like that. They
expect clocks
coming from global clock nets (GBUF for Xilinx). You have only a few of these.
I have another idea:
Write a D-flip-flop with R/S module and instantiate it in your design. Make everything
synchronous
to ONE system clock. DON'T use asynchronous stuff. FPGA can do real latches, but
everybody
(including the tools) start yelling if you do that....
I attach a code snippet..
Best wishes,
Philipp :-)
--
http://www.hachti.de
You definitely need the "reset" that the CAF
instruction (and the
"clear" key on an 8/e triggers). For an 8/i, it's BINITIALIZE,
which is triggered by the "start" key on the front panel.
Will add that -
currently there is no proper CAF instruction *g* - Will be built in...
If multiple IO
devices are to be connected, the IN lines (to the CPU)
must be OR'ed together.
The original PDP-8's have these active low, and a logical OR is
implemented with wire-and, via open-collector drivers. When my
project is in a usable state, I would like to put it on
opencores.org.
Cool! It might be an interesting point to work from for what Henk
and I are trying to do. VHDL or
Verilog code?
VHDL. > How is it attached? Shift registers?
How is
the front panel attached to the rest of the system?
Most of them -- Skips are never skipping, and all IOTs
clear AC.
Shouldn't be too hard to fix, but I haven't really looked into
it yet.
I would love to take a glance at the code...!!
I have recently started to implement a "direct
coding" of the 8/i
schematics in VHDL. That will hopefully give a "clock accurate"
implementation of the 8/i.
What a task!!!
If you try the real thing, you will get lots of angry warnings about
flip flop clock input abuse! DEC used the D-flip flops with preset and
clear in a (today) very uncommon way....!