Lack of robustness with 1K and 4K RAM chips (was Re: 2116 and other old memory chips)

see below, plz. Dick ----- Original Message ----- From: "Ethan Dicks" &lt;ethan_dicks(a)yahoo.com&gt; To: &lt;classiccmp(a)classiccmp.org&gt; Sent: Friday, July 06, 2001 11:43 PM Subject: Re: Lack of robustness with 1K and 4K RAM chips (was Re: 2116 and other old memory chips) <snip> It would have been difficult for them to do, since the CPU didn't have that capability. The Z80 had a hardware refresh cycle built into its operating circuitry. It had a refresh counter (though only 7 bits) which was placed on the address bus while the CPU decoded an opcode. The XC68000 was the designator for the earliest units, primarily engineering samples of the various masks, though mine, (1978-79) from an early mask design later obsoleted, were marked with the MC68000 designation and a mask number. One of these had bus timing spec's that allowed it to operate at speeds exceeding those of later masks at nearly twice the clock rate. Anything's possible, but MOT didn't publish anything about this feature in the various engineering notes the published to characterize the various masks they produced. Since the original plans were to use the MC68K with cache, support for DRAM refresh would probably have gotten in the way. Within months of the release of the 68K, 64K DRAMs that worked as fast as the MC68K could digest the data became available, and, as the decision had been made to abandon the masks with timing capable of exceeding the timing for those devices, cacheless DRAM-based memory systems could be designed to run at full speed.