hi
on DTB we are designing a RISC-ish CPU, code name "Arise-v2"(1).
We are using the MIPS R2K and the RISC-V as the reference.
In the end, it will be implemented in HDL -> FPGA.
The page on DTB is related to a software emulator (written in C) for
the whole system. CPU + RAM + ROM + UART, etc. so we can test and our
ISA more comfortably.
As a second reference, I'd like to consider the first Motorola RISC:
88K, which is very elegant and neat ISA; unfortunately, I have
difficulties at finding user manuals and books about it.
If someone wants to sell me a copy, it will be appreciated!
Thanks and happy new year!
p.s.
other interesting contributes about RISC-V and architectures, are on
this (2) EEVBlog's topic
(1)http://www.downthebunker.xyz/wonderland/reloaded/bazaar/viewtopic.php?f=36&t=194&sid=5294ee174485ac7863eedd496108c996
(
2)https://www.eevblog.com/forum/microcontrollers/risc-v-assembly-language-p…