17 Jun
2011
17 Jun
'11
11 p.m.
~http://www.rogtronics.net
On Sat, Jun 18, 2011 at 1:17 AM, Alexey Toptygin <alexeyt at freeshell.org>wrote:
It's still glitchless providing you don't abuse the gates timing, as
with
any logic can be made to glitch by abusing the timing. You can make a 7486
glitch too, just by abusing the setup time - it doesn't have an infinite
operating frequency.
On Fri, 17 Jun 2011, Chuck Guzis wrote:
Yes, but I don't see what that has to do with the thread. If you're
it doesn't, I was just answering your "query" about XOR gates :) In fact,
it
relates to transistor logic, instead of SSI logic. Where the same transistor
circuit can be repeated and wired in a manner to produce a XOR gate - using
only 4 transistors - and a few diodes :) This is one of the things I showed
in my Transistor Logic workshop at VCF East.
Although probably every undergrad
going to dedicate a whole quad NAND package to a
single 2-input-XOR,
that's not terribly efficient.
computer logic
professor has pointed out this "neat trick" in class
for the last 40+ years, I don't believe it's glitchless, so it's not
a really good choice.
By 'not glitchless' do you mean that if you simultaneously change the
inputs from 00 to 11 you'll see an approx. 1 gate delay wide transient on
the output of the XOR due to some of the signals passing through 2 and some
through 3 NANDs?
no, that won't make it glitch. If you make a timing diagram , you can see
this(even with a liberal gate delay, say , 10nsec - that fits even on graph
paper) . Even though the 1st nand gate will change levels, the middle 2 nand
gates are still unchanged since they don't enter a true state. So the 4th
nand gate remains at a logic 0. This is also true if the states change from
00 -> 01 or 00->10. Even with 11->01 or 11->10. The 4th nand gate is always
the sum of both middle nand gates - including their gate delays.
Is there a way to build an XOR from other types of gates that won't glitch
on any of the input transitions 00 <-> 11 or 10 <-> 01 ? Even if you
can't
guarantee that all the gate delays are the same?
like I mentioned about the 7486, you can make that glitch or any other part
if you don't observe the timing parameters.
=Dan