22 May
2013
22 May
'13
11:39 a.m.
On 05/22/2013 09:33 AM, allison wrote:
On 05/22/2013 07:28 AM, Vince Mulhollon wrote:
8080 code that does that:
; read case
;
; we have 16us to do a read and wait for the next
; so tricks are used to save cycles.
; At 2mhz we have 32 cycles (8080 2mhz case).
; Registers used.
; Acc is IO
; C is bytecount/4
; DE ram write pointer
; we repeat the input operation 4x so the
; a few cycles are saved on the byte count test
; and we can run sectors to 1024 using a single register.
;
; Assumptions, no memory wait states
; DRAM is NOT used, unless self refreshing
; without wait states.
;
; For a z80 not all the Z80 instructions run faster
; so any modification to use z80 insturcitons have
; to be very carefully picked.
;
loop: IN fdcportwait ;10cy
STAX D ;10cy
INX D ;7cy
DCR C ;4cy
; by causing wait on read data available in hardware we save
; a test for data ready and make it with 1 cycle extra.
IN fdcportwait
STAX D
INX D
DCR C
IN fdcportwait
STAX D
INX D
DCR C
IN fdcportwait
STAX D
INX D
DCR C
JNZ LOOP ; 10cy for jump, puts us
close be the system works as
; our read will
happen soon as we get there if data is
; already
waiting. Also it helps if the 8080 is pushed
;
18.432mhz/9=2.048mhz=.488us Tcy
; Most 8080s
will run at 2.5mhz!
Note on a z80 at 2,5mhz or a 8085 at 2.5mhz or faster this works easily.
On an 8080 it works but is very close timing wise. NOTE that even the
slowest 8085 is 3mhz and the slowest z80 is 2.5mhz. If the system is
running at 2mhz for those it may be ok but slower clock is NOT possible.
Allison
On Tue, May 21, 2013 at 4:39 PM, Chuck Guzis
<cclist at sydex.com> wrote:
Actually you have 16us to complete the
transfer. It can be done even
with 8080
but the software loop must assume the in or out has a implied wait
(stall)
to keep the loop tight enough to keep up...
The problem is two fold, one if the data ready/request never happens
(open door/no media)
the system is hung.
The other is if your using DRAM you are not refreshing in that state
so a hang or long delay
(like waiting a full revolution for the sector) will likely crash the
system on ram errors.
Interrupts during that time will be pending till the wait is released.
I have done it with 3mhz 8085 easily and 4mhz Z80 this way.
A few years back, Herb Johnson opened a
discussion of this on his web
site. The conclusion was that a 4 MHz Z80 was indeed fast enough to do
this with programmed I/O and DD 8" disks (500KHz data rate) and that
it was
*barely* possible to do at 2 MHz Z80 set up correctly and not at all
with a
2 MHz 8080.
There are hardware issues also relating to your selection of FDC. The
general consensus and experience of the N8VEM CP/M board builders is
that
programmed IO with a 8 MHz and up Z80 and a modern 1.44 MHz floppy and a
9266 FDC works perfectly. I assembled a system this winter and that
worked
perfectly. Obtaining 8+ MHz chips for modern Z80 designs is non trivial
and involves lots of ebay and searching.
Someday I will remove my CPU canned osc, locate a TTL output function
generator, and figure out exactly what the minimum is. The disk io v3
board has headers and software support for a 8 inch floppy and if I can
locate one I could do pretty extensive testing of different disk
technologies. This type of test with a live system, lots of different
drive types, and a ttl output function generator in place of CPU clock
would certainly prove once and for all what is required for what drive
technology.
The minimum is:
Assumes a FDC read or write will pull /wait until the FDC
clears it with a data request.
Read or write a byte,
Index to zero byte count
index ram pointer
get next byte in the Acc
jump to start if not zero