FPGA VAX update

Yep, 86xx was ECL10k and a little of the early ECLx (early next generation). The 9000 was the ECL100K+ packaging. So an 86xx was still above 10nS for a full adder with lookahead. There is also something that came out of the RISC camp. The more stuff running in (hopefully) lockstep (multiple microengines) the more work on timing margins needs to be done. Critical paths for logic dominate and system speed will be slower. the MicroVAX-I was almost the other end of the spectrum. It was almost how much can be taken out and still be a creditable vax. That simplification was an important clue for the VAX on silicon (uV-II) as to hove much had to be there and how fast. I'd think if you simplify the 780 to eliminate the busses other than local ones and then implement using new tech the scalar result could be quite fast. However if the goal is to make a 780 with all the busses common to it for the IO and storage you'll end up with a more logic to implement the busses than the core CPU in hardware. One look at the microVAX series will show even though the cpu was reduced to trivial number of chips the total board space wraped around it was for busIO. the best contrast is the uVaxII (qbus) and the uVAX2000. They are close in performance (exact same CPU) but miles apart in power needed and chip count. This pattern occurs throughout the industry with just about every cpu that comes to mind. Allison