SC/MP 8073 addressing query

Hi list, I have an interesting question regarding the INS8073 (National Semiconductor SC/MP 3 with BASIC in ROM). Finally, somebody gave me a round tuit, and I have started work on a simple 8073 system. Eventually, it will have 8K of ROM, 8K of RAM, an 8255, and a switch / LED interface. Currently on the board, I have the 6264 RAM tied to the 8073, with no address decoding (ie the CS* on the RAM is tied to A15 on the CPU). Sadly, as a simple test, this does not operate as I would expect. I would have expected that the RAM would have been selected anywhere in the lower 32K or the memory map, and I would have a simple system that would spit out a console prompt. But no luck. Now the question.... The internal ROM is located in the lowest 4K or the memory map. When the CPU is fetching data from the lower 4K, does it assert the NRDS line, and sample the external bus? My belief is that it does not, as the trivial application note that I have seen simply ties a couple of 2114 to the processor, and uses A10 as the chip select. Any ideas? Doug -- Doug Jackson, I-RAP, MAIPM, MIEEE Principal Information Security Consultant EWA-AUSTRALIA PO Box 6308 O'Connor ACT 2602 Level 1, 214 Northbourne Ave, Braddon ACT 2612 Tel: +61 (0)2 6230 6833 Fax: +61 (0)2 6230 5833 Mob: +61 (0)414 986 878 http://www.ewa-australia.com ============================================ IMPORTANT: This email remains the property of Electronic Warfare Associates - Australia. If you have received this email in error, you are requested to contact doug.jackson at ewa-australia.com or Ph +61 2 62306833 and delete the email. This message is not to be copied or distributed to other parties without the express permission of the author. Any personal information in this email must be handled in accordance with the Privacy Act 1988 (Cth). ============================================