Antonio wrote:
I've never had to interface to SDRAM, so I cannot
say how hard it
is. But the data sheets are readily available.
"Plain" SDRAM is not too hard to deal with (only slightly more complex
than the older FPM and EDO DRAM), and uses ordinary 3.3V CMOS
levels, though parts intended for "mobile" use may use 1.8V or 2.5V
CMOS levels.
DDR, DDR2, DDR3, etc. use the "Stub Series Terminated Logic" (SSTL)
I/O standards that are not compatible with normal logic levels. As a
consequence, they are relatively difficult to interface.
http://en.wikipedia.org/wiki/Stub_Series_Terminated_Logic
Typically DDR SDRAM is connected directly to a processor or north bridge
with an embedded controller and drivers. Most Xilinx FPGAs have I/O
buffers that can be configured for SSTL.
Eric