28 Jul
2007
28 Jul
'07
7:28 a.m.
From: "Dave Dunfield" <dave06a at
dunfield.com>
Hi
One other thing. Ususally one doesn't see this one but on a machine I
put together, using a different processor, on one command I was
able to beet the busy response of the controller chip. It was on only
one command but I don't recall which command.
If the PC is running the bus faster than the 765 is clocking, one can
be too quick.
I recall putting a short delay to make sure the status read was coorrect.
I know it was this because I did an experiment that I'd read it twice.
The second read was OK but not the first.
Dwight
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Ah, the step gremlin. It's an old
765(all!!!) problem. The problem is
when
the step pulse is set to minimum acceptable for
the drive it's possible
that
due to internal timing of the 765 it can shorten
the step timing of the
first pulse by 1 count. If that occurs many drives seek badly and you
get
read or write errors because your not where you
thought you were.
Note: some old drives due to the lubricants turning to goo will also
exhibit
this type of error. There is one solution, step
slower (SRT+1).
A possibility - Christial, try using SR= to set the step rate slower.