ISO: PDP-11/40 LTC and Stack Limit options

Well, the BG4-BG7 grants definitely _are_ run through the SPC slot 9 (see below) - at least, on a stock system. It's _possible_ that the software you're loading doesn't use interrupts. (I have this vague memory that, unlike the -11/34, the /40 doesn't complain if there's a non-continuous grant line.) Or perhaps someone wired them across on that slot, to avoid knuckle-mashing trying to put a G727 down there. Anyway, the wire list in the drawings show all four lines (although they are listed in two places, under "BGx" and "BUS BGx"). E.g. BG4 is shown on pg. 79 as going from D07E2 (Source - K4-6, pg. 63, top right) to D09S2 (which is the correct BG4 'in' pin for SPC), and as BUS BG4 on pg. 84 as going from D09T2 (SPC BG4 'out' pin) to B09E2 (correct BG4 UNIBUS 'out' pin). Yahh!! Right, BG6 is wired through that KW11-L slot because the clock needs interrupts - the wire list shows that on pg. 79, where the BG6 entry is longer than the other BGn entries, because of that. If I'm reading the notations correctly, it shows the jumper installed by default - I guess it was removed by hand on systems sold with a KW11-L? There must also be some way to indicate that the jumper should be wired on top at both ends (so the F03V2 to D09M2 wire wouldn't have to be removed to pull the F03R2 to F03V2 jumper) - although maybe they just did _all_ multi-pin runs as alternating low on both ends, high on both ends, repeat to make removal/replacement easier. Speaking of notation, dunno if you knew this (I didn't), but the wire list for the 11/40 includes etch also; you can tell etch entries from an 'H' in the "Q" column and 'P' in the "Remark" column. Don't confuse them with the 'H' in the "A/P" column, which also also has some 'L' entries; not sure what that is about, unless it tells whether the signal is asserted high or low. Noel