29 Dec
2008
29 Dec
'08
11:02 p.m.
On Dec 29, 2008, at 2:44 PM, Alexandre Souza wrote:
If there's enough interest, I'll try for it since I'm doing a unibus
memory board (a multifunction board) with an FPGA for everything but
the memory and interfaces. I'd have to look at the interface from the
cache boards, but I might be tempted to use SSRAMs since they can be
obtained in wide bit widths (36 bits) in a single chip and aren't too
difficult to interface to (timing wise). I know that they come in
512K x 36 since I'm considering that for another project. So that
would only require 2 parts for the entire memory array (4MB). If ECC
were required, there'd be a bit more involved and I'd have to look to
see what was available.
However, I'm swamped with my real job and haven't had a lot of time
(read none) to spend on this stuff. I've already done the schematic
capture for the Unibus interface and level shifters and I'm about
15-20% done coding up the verilog for the FPGA. I've done all of the
high level design, memory timing and unibus address decode. The rest
is the internal interconnect, serial, unibus state machine and
configuration state machine plus the individual unibus devices
(memory, KW11L, ROMs, 2 SLUs).
TTFN - Guy
I do not know
nearly enough to contemplate designing a board to
imitate the entire MK11 and a stack of memory. The memory is the
simple part. The idea of mating a RAM field with a Spartan 3 FPGA
sounds entirely workable, but I wouldn't know how to bring it all
together nor what to stuff in the FPGA to make it all magically work.
Nor do I, but it would be something interesting :o)